Field of the Disclosure
The present disclosure relates to an array substrate for a liquid crystal display device (LCD), and more particularly, to an array substrate for an LCD including a coplanar type thin film transistor (TFT) and a method of manufacturing the same.
Discussion of the Prior Art
With the advancement of information society, demand for a display device capable of displaying an image has increased in various forms. Recently, various flat panel display devices, such as a liquid crystal display device (LCD), a plasma display panel (PDP), and an organic light emitting diode display (OLED), have been used.
Among these flat panel display devices, the LCD has advantages of low power consumption due to low driving voltage and portability, and thus is widely used in various fields, such as laptop computer, monitor, spacecraft, and airplane.
Particularly, an active matrix LCD device in which a thin film transistor (TFT) as a switching element is formed in each of pixels arranged in a matrix has been commonly used.
The TFT are categorized into various types according to positions of a gate electrode, for example, a staggered type, an inverted staggered type, and a coplanar type.
The coplanar type TFT has excellent element property because an active layer thereof is not damaged when etching source and drain electrodes.
The coplanar type TFT has a structure that a gate electrode, and the source and drain electrodes are located over the active layer.
FIG. 1 is a cross-sectional view illustrating the coplanar type TFT according to the prior art.
Referring to FIG. 1, a buffer layer 11 is formed on a substrate 10. An active layer 24 is formed on the buffer layer 11 and includes a channel region 24a and source and drain regions 24b and 24c at both sides, and a first insulating layer 15a is formed on the active layer 24.
A gate electrode 21 is formed on the first insulating layer 15a, and a second insulating layer 15b is formed on the gate electrode 21 and includes contact holes exposing the source and drain regions 24b and 24c. Source and drain electrodes 22 and 23 are formed on the second insulating layer 15b and contact the source and drain regions 24b and 24c, respectively.
The active layer 24, the gate electrode 21, and the source and drain electrodes 22 and 23 as above form a coplanar type TFT.
A third insulating layer 15c is formed on the source and drain electrodes 22 and 23 and includes a contact hole exposing the drain electrode 23. A pixel electrode 18 is formed on the third insulating layer 15c and contacts the drain electrode 23.
The active layer 24 is made of a ZnO based semiconductor material, thus has a high mobility and meets a constant current test condition, and thus is applicable to a large-sized display.
The ZnO is a material that can have a conductor property, a semiconductor property, or a nonconductor property according to a content of oxygen. Accordingly, the active layer using the ZnO is applicable to a large-sized display, for example, LCD or OLED.
However, the second insulating layer 15b is formed to prevent the active layer 24 of the ZnO based material from being exposed, and thus a number of mask processes increases.
Thus, steps of production processes increase, thus production cost increases, and productivity decreases.